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ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 6 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
DSD
2009
IEEE
145views Hardware» more  DSD 2009»
15 years 11 months ago
High Performance Image Processing on a Massively Parallel Processor Array
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bru...
ISMAR
2007
IEEE
15 years 10 months ago
Accelerating Template-Based Matching on the GPU for AR Applications
Recently researchers have shown that it is possible to use GPU hardware for image processing and computer vision algorithms. We have been exploring how to use GPU hardware to impr...
Yannick Allusse, Raphael Grasset, Mark Billinghurs...
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
15 years 10 months ago
Faster exploration of high level design alternatives using UML for better partitions
Partitioning is a time consuming and computationally complex optimization problem in the codesign of hardware software systems. The stringent time-to-market requirements have resu...
Waseem Ahmed, Doug Myers
DATE
2005
IEEE
197views Hardware» more  DATE 2005»
15 years 9 months ago
picoArray Technology: The Tool's Story
This paper briefly describes the picoArrayTM architecture, and in particular the deterministic internal communication fabric. The methods that have been developed for debugging a...
Andrew Duller, Daniel Towner, Gajinder Panesar, Al...