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ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
15 years 8 months ago
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance
A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors...
Zhaozhi Yang, Zeyi Wang, Shuzhou Fang
ERSA
2009
91views Hardware» more  ERSA 2009»
15 years 2 months ago
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors
Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dynamically Reconfigurable Processors (DRPs). By using a prepared configu...
Toru Sano, Yoshiki Saito, Hideharu Amano
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 10 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
FCCM
2005
IEEE
102views VLSI» more  FCCM 2005»
15 years 10 months ago
A Signature Match Processor Architecture for Network Intrusion Detection
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructu...
Janardhan Singaraju, Long Bu, John A. Chandy
IEEEPACT
2003
IEEE
15 years 9 months ago
Reactive Multi-Word Synchronization for Multiprocessors
Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hard...
Phuong Hoai Ha, Philippas Tsigas