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ARITH
2003
IEEE
15 years 9 months ago
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latenc...
Soonhak Kwon
ISWC
2003
IEEE
15 years 9 months ago
MIThril 2003: Applications and Architecture
In this paper we describe the MIThril 2003 wearable computing research platform. MIThril 2003 is a proven, accessible architecture that combines inexpensive, commodity hardware, a...
Richard W. DeVaul, Michael Sung, Jonathan Gips, Al...
ICPP
2000
IEEE
15 years 9 months ago
Partial Resolution in Data Value Predictors
Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level parallelism (ILP). An outcome of an instructio...
Toshinori Sato, Itsujiro Arita
IPPS
1998
IEEE
15 years 8 months ago
NTI: A Network Time Interface M-Module for High-Accuracy Clock-Synchronization
This paper? provides a description of our Network Time Interface M-Module NTI supporting high-accuracy external clock synchronization by hardware. The NTI is built around our custo...
Martin Horauer, Ulrich Schmid, Klaus Schossmaier
DAC
1998
ACM
15 years 8 months ago
A Geographically Distributed Framework for Embedded System Design and Validation
The di culty of embedded system co-design is increasing rapidly due to the increasing complexity of individual parts, the variety of parts available and pressure to use multiple p...
Ken Hines, Gaetano Borriello