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ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
15 years 11 months ago
Image sensor with focal plane change event driven video compression
— An image sensor with focal plane based hardware acceleration of video compression is presented. The 90×90 pixel CMOS image sensor provides in-pixel processing of intensity cha...
Yu M. Chi, Ralph Etienne-Cummings, Gert Cauwenberg...
AHS
2007
IEEE
277views Hardware» more  AHS 2007»
15 years 11 months ago
Maxwell - a 64 FPGA Supercomputer
We present the initial results from the FHPCA Supercomputer project at the University of Edinburgh. The project has successfully built a general-purpose 64 FPGA computer and porte...
Robert Baxter, Stephen Booth, Mark Bull, Geoff Caw...
ASAP
2007
IEEE
169views Hardware» more  ASAP 2007»
15 years 11 months ago
Reduced Delay BCD Adder
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
A. A. Bayrakci, A. Akkas
141
Voted
ASAP
2007
IEEE
93views Hardware» more  ASAP 2007»
15 years 11 months ago
LNS Subtraction Using Novel Cotransformation and/or Interpolation
The Logarithmic Number System (LNS) makes multiplication, division and powering easy, but subtraction is expensive. Cotransformation converts the difficult operation of logarithm...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
132
Voted
DDECS
2007
IEEE
143views Hardware» more  DDECS 2007»
15 years 11 months ago
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
Pavel Kubalík, Jirí Kvasnicka, Hana ...