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102
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APCCAS
2002
IEEE
15 years 9 months ago
2002
IEEE
The pyramid networks are well-known as suitable structures for parallel computations such as image processing. This paper shows a practical 3D VLSI layout of the N-vertex pyramid ...
121
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
118
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
115
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
The minimization of cost, power consumption and timeto-market of DSP applications requires the development of methodologies for the automatic implementation of floating-point alg...
126
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...