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DEPCOS
2008
IEEE
180views Hardware» more  DEPCOS 2008»
15 years 11 months ago
A Resilient SIL 2 Driver Machine Interface for Train Control Systems
In railway train-borne equipment, the Driver Machine Interface (DMI) acts like a bridge between the train driver and the onboard automatic train control system (European Vital Com...
Andrea Ceccarelli, István Majzik, Danilo Io...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
15 years 11 months ago
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
IEEEPACT
2007
IEEE
15 years 11 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
15 years 11 months ago
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint
— Multiview video coding (MVC) systems require much more bandwidth and computational complexity relative to mono-view video systems. Thus, when designing a VLSI architecture for ...
Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi ...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
15 years 11 months ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl