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ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
15 years 8 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
CODES
2001
IEEE
15 years 8 months ago
Modeling and evaluation of hardware/software designs
We introduce the foundation of a system modeling environment targeted at capturing the anticipated interactions of hardware and software behaviors -- not just their co-execution. ...
Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas
128
Voted
ARC
2010
Springer
186views Hardware» more  ARC 2010»
15 years 8 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
EUROPDS
1997
15 years 6 months ago
A Combined Virtual Shared Memory and Network which Schedules
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
Ronald Moore, Bernd Klauer, Klaus Waldschmidt
172
Voted
ECRTS
2009
IEEE
15 years 2 months ago
Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies
This paper explores timing anomalies in WCET analysis. Timing anomalies add to the complexity of WCET analysis and make it hard to apply divide-and-conquer strategies to simplify ...
Raimund Kirner, Albrecht Kadlec, Peter P. Puschner