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IPPS
2002
IEEE
15 years 11 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
MICRO
2002
IEEE
122views Hardware» more  MICRO 2002»
15 years 11 months ago
Microarchitectural denial of service: insuring microarchitectural fairness
Simultaneous multithreading seeks to improve the aggregate computation bandwidth of a processor core by sharing resources such as functional units, caches, TLB and so on. To date,...
Dirk Grunwald, Soraya Ghiasi
155
Voted
FPL
2009
Springer
79views Hardware» more  FPL 2009»
15 years 11 months ago
A reconfigurable architecture for the Phylogenetic Likelihood Function
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
Nikolaos Alachiotis, Alexandros Stamatakis, Euripi...
SAMOS
2009
Springer
15 years 10 months ago
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems...
Yahya Jan, Lech Józwiak
ICCAD
2000
IEEE
100views Hardware» more  ICCAD 2000»
15 years 10 months ago
Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits
In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-underte...
Sudip Chakrabarti, Abhijit Chatterjee