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DATE
2009
IEEE
172views Hardware» more  DATE 2009»
16 years 1 months ago
On bounding response times under software transactional memory in distributed multiprocessor real-time systems
We consider multiprocessor distributed real-time systems where concurrency control is managed using software transactional memory (or STM). For such a system, we propose an algori...
Sherif Fadel Fahmy, Binoy Ravindran, E. Douglas Je...
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
16 years 1 months ago
Sequential logic synthesis using symbolic bi-decomposition
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
Victor N. Kravets, Alan Mishchenko
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
16 years 1 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
DATE
2009
IEEE
85views Hardware» more  DATE 2009»
16 years 1 months ago
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
CSCWD
2009
Springer
16 years 28 days ago
Random stimulus generation with self-tuning
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong