We have developed Argus, a novel approach for providing low-cost, comprehensive error detection for simple cores. The key to Argus is that the operation of a von Neumann core cons...
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
We present an algorithm for generating panoramic images of complex scenes from a multi-sensor camera. We further present a programmable graphics hardware implementation to process...
—In this paper, an area/delay efficient recoding method for parallel CORDIC (COordinate Rotation DIgital Computer) rotation algorithm is proposed. This recoding method can reduce...