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MICRO
2007
IEEE
94views Hardware» more  MICRO 2007»
16 years 20 days ago
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
We have developed Argus, a novel approach for providing low-cost, comprehensive error detection for simple cores. The key to Argus is that the operation of a von Neumann core cons...
Albert Meixner, Michael E. Bauer, Daniel J. Sorin
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
16 years 19 days ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
16 years 19 days ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
3DPVT
2006
IEEE
176views Visualization» more  3DPVT 2006»
16 years 13 days ago
Belief Propagation for Panorama Generation
We present an algorithm for generating panoramic images of complex scenes from a multi-sensor camera. We further present a programmable graphics hardware implementation to process...
Alan Brunton, Chang Shu
APCCAS
2006
IEEE
261views Hardware» more  APCCAS 2006»
16 years 13 days ago
Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations
—In this paper, an area/delay efficient recoding method for parallel CORDIC (COordinate Rotation DIgital Computer) rotation algorithm is proposed. This recoding method can reduce...
Tso-Bing Juang