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APCSAC
2006
IEEE
16 years 14 days ago
Issues and Support for Dynamic Register Allocation
Abstract. Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of r...
Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
16 years 14 days ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
16 years 14 days ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
DATE
2006
IEEE
103views Hardware» more  DATE 2006»
16 years 14 days ago
Novel designs for thermally robust coplanar crossing in QCA
In this paper, different circuit arrangements of Quantumdot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. These arrangements exploit the majority votin...
Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, ...
DATE
2006
IEEE
145views Hardware» more  DATE 2006»
16 years 14 days ago
Building a better Boolean matcher and symmetry detector
Boolean matching is a powerful technique that has been used in technology mapping to overcome the limitations of structural pattern matching. The current basis for performing Bool...
Donald Chai, Andreas Kuehlmann