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155
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CODES
2005
IEEE
16 years 1 days ago
Energy conscious online architecture adaptation for varying latency constraints in sensor network applications
Sensor network applications face continuously changing environments, which impose varying processing loads on the sensor node. This paper presents an online control method which a...
Sankalp Kallakuri, Alex Doboli
159
Voted
DATE
2005
IEEE
224views Hardware» more  DATE 2005»
16 years 1 days ago
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially ...
David C. Keezer, C. Gray, A. M. Majid, N. Taher
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
16 years 1 days ago
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parame...
Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, S...
152
Voted
DATE
2005
IEEE
97views Hardware» more  DATE 2005»
16 years 1 days ago
Efficient Solution of Language Equations Using Partitioned Representations
A class of discrete event synthesis problems can be reduced to solving language equations F • X ⊆ S, where F is the fixed component and S the specification. Sequential synthes...
Alan Mishchenko, Robert K. Brayton, Jie-Hong Rolan...
180
Voted
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
16 years 1 days ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles