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SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
15 years 11 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
SBACPAD
2003
IEEE
121views Hardware» more  SBACPAD 2003»
15 years 11 months ago
Optimizing Packet Capture on Symmetric Multiprocessing Machines
Traffic monitoring and analysis based on general purpose systems with high speed interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, requires carefully designed software...
Gianluca Varenni, Mario Baldi, Loris Degioanni, Fu...
SBACPAD
2003
IEEE
137views Hardware» more  SBACPAD 2003»
15 years 11 months ago
Exploring Memory Hierarchy with ArchC
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
SBACPAD
2003
IEEE
103views Hardware» more  SBACPAD 2003»
15 years 11 months ago
Performance Analysis Issues for Parallel Implementations of Propagation Algorithm
This paper presents a theoretical study to evaluate the performance of a family of parallel implementations of the propagation algorithm. The propagation algorithm is used to an i...
Leonardo Brenner, Luiz Gustavo Fernandes, Paulo Fe...
138
Voted
ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
15 years 11 months ago
Synthesis and placement flow for gain-based programmable regular fabrics
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gainbased Logic Blocks (GLBs). The GLB is a semi-univers...
Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek...