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DATE
2000
IEEE
75views Hardware» more  DATE 2000»
15 years 11 months ago
Layout Compaction for Yield Optimization via Critical Area Minimization
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
Youcef Bourai, C.-J. Richard Shi
171
Voted
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 11 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
DATE
2000
IEEE
87views Hardware» more  DATE 2000»
15 years 11 months ago
Multi-Node Static Logic Implications for Redundancy Identification
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
Kabir Gulrajani, Michael S. Hsiao
158
Voted
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
15 years 11 months ago
Meeting Delay Constraints in DSM by Minimal Repeater Insertion
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints. We use mini...
I-Min Liu, Adnan Aziz, D. F. Wong
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
15 years 11 months ago
Quantitative Comparison of Power Management Algorithms
Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated effective in certain applications. We quantit...
Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, G...