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ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
15 years 10 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
ISPD
1999
ACM
106views Hardware» more  ISPD 1999»
15 years 10 months ago
Timing driven maze routing
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Sung-Woo Hur, Ashok Jagannathan, John Lillis
EH
1999
IEEE
140views Hardware» more  EH 1999»
15 years 10 months ago
On the Filtering Properties of Evolved Gate Arrays
A small gate array is evolved extrinsically to carry out a low pass filtering task defined over fifteen different frequencies. The circuit is evolved by assessing its response to ...
Julian F. Miller
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 10 months ago
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity ...
Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Ji...
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
15 years 10 months ago
Design and optimization of LC oscillators
We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial...
Maria del Mar Hershenson, Ali Hajimiri, Sunderaraj...