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ASPDAC
2007
ACM
89views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Trace Compaction using SAT-based Reachability Analysis
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
Sean Safarpour, Andreas G. Veneris, Hratch Mangass...
ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Advanced tools for simulation and design of oscillators/PLLs
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
Xiaolue Lai, Jaijeet S. Roychowdhury
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Fault Dictionary Size Reduction for Million-Gate Large Circuits
- In general, fault dictionary is prevented from practical applications for its extremely large size. Several previous works are proposed for the fault dictionary size reduction. H...
Yu-Ru Hong, Juinn-Dar Huang
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
15 years 10 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
CAV
2007
Springer
145views Hardware» more  CAV 2007»
15 years 10 months ago
Hybrid Systems: From Verification to Falsification
We propose HyDICE, Hybrid DIscrete Continuous Exploration, a multi-layered approach for hybrid-system testing that integrates continuous sampling-based robot motion planning with d...
Erion Plaku, Lydia E. Kavraki, Moshe Y. Vardi