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ATS
2001
IEEE
137views Hardware» more  ATS 2001»
15 years 10 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 10 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
IWMM
2000
Springer
135views Hardware» more  IWMM 2000»
15 years 10 months ago
Conservative Garbage Collection for General Memory Allocators
This paper explains a technique that integrates conservative garbage collection on top of general memory allocators. This is possible by using two data structures named malloc-tab...
Gustavo Rodriguez-Rivera, Michael Spertus, Charles...
ASAP
1997
IEEE
92views Hardware» more  ASAP 1997»
15 years 10 months ago
Optimized software synthesis for synchronous dataflow
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward...
ASYNC
1997
IEEE
103views Hardware» more  ASYNC 1997»
15 years 10 months ago
Efficient Timing Analysis Algorithms for Timed State Space Exploration
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
Wendy Belluomini, Chris J. Myers