7262 search results - page 632 / 1453 » Reversible Computer Hardware |
249
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CPE
1994
Springer
15 years 11 months ago
1994
Springer
When implementingparallel programs forparallel computer systems the performancescalability of these programs should be tested and analyzed on different computer configurations and...
183
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ICCAD
2007
IEEE
2007
IEEE
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
15 years 10 months ago
Abstract: Polynomial computations over fixed-size bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositi...
179
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
168
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EUROPAR
2008
Springer
15 years 8 months ago
2008
Springer
Abstract. With the emergence of multi-core CPU (or Chip-level MultiProcessor -CMP-), it is essential to develop techniques that capitalize on CMP's advantages to speed up very...
217
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increa...