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ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
16 years 14 days ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
16 years 14 days ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ISCA
2005
IEEE
81views Hardware» more  ISCA 2005»
16 years 13 days ago
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores...
Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upt...
ISCAS
2005
IEEE
156views Hardware» more  ISCAS 2005»
16 years 13 days ago
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due...
Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubm...
240
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ISPD
2005
ACM
249views Hardware» more  ISPD 2005»
16 years 12 days ago
APlace: a general analytic placement framework
We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored the adaptability of A...
Andrew B. Kahng, Sherief Reda, Qinke Wang