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EH
2000
IEEE
183views Hardware» more  EH 2000»
15 years 11 months ago
A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
Ricardo Salem Zebulum, Cristina Costa Santini, Hel...
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
15 years 11 months ago
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
IJCNN
2000
IEEE
15 years 11 months ago
Design and Evaluation of Neural Networks for Coin Recognition by Using GA and SA
In this paper, we propose a method to design a neural network(NN) by using a genetic algorithm(GA) and simulated annealing(SA). And also, in order to demonstrate the effectivenes...
Yasue Mitsukura, Minoru Fukumi, Norio Akamatsu
VISUALIZATION
2000
IEEE
15 years 11 months ago
Combining local and remote visualization techniques for interactive volume rendering in medical applications
For a comprehensive understanding of tomographic image data in medical routine, interactive and high–quality direct volume rendering is an essential prerequisite. This is provid...
Klaus Engel, Thomas Ertl, Peter Hastreiter, Bernd ...
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
15 years 11 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge