287 search results - page 12 / 58 » Reversible logic circuit synthesis |
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
CASES
2001
ACM
15 years 1 months ago
2001
ACM
We describe a digital circuit synthesis algorithm specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use this algorithm as ...
CF
2007
ACM
15 years 1 months ago
2007
ACM
This paper presents the Collapsed Bennett Layout, a general purpose floorplan for reversible quantum-dot cellular automata (QCA) circuits. In order to exploit the full density and...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...