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» Reversible logic circuit synthesis
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DAC
1994
ACM
15 years 2 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
15 years 10 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
CCL
1994
Springer
15 years 2 months ago
Application of Constraint Logic Programming for VLSI CAD Tools
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
Renate Beckmann, Ulrich Bieker, Ingolf Markhof
ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
14 years 12 months ago
Decomposition based approach for synthesis of multi-level threshold logic circuits
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
Tejaswi Gowda, Sarma B. K. Vrudhula
ICCAD
1997
IEEE
142views Hardware» more  ICCAD 1997»
15 years 2 months ago
Library-less synthesis for static CMOS combinational logic circuits
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullel...