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» Reversible logic circuit synthesis
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ITC
1998
IEEE
114views Hardware» more  ITC 1998»
15 years 2 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
15 years 1 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
15 years 2 months ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
CAV
2010
Springer
286views Hardware» more  CAV 2010»
14 years 10 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
15 years 3 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...