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» Reversible logic circuit synthesis
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ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
15 years 3 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
DAC
2007
ACM
15 years 11 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 2 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISMVL
2003
IEEE
68views Hardware» more  ISMVL 2003»
15 years 3 months ago
Multi-Output Galois Field Sum of Products Synthesis with New Quantum Cascades
Galois Field Sum of Products (GFSOP) leads to efficient multi-valued reversible circuit synthesis using quantum gates. In this paper, we propose a new generalization of ternary To...
Mozammel H. A. Khan, Marek A. Perkowski, Pawel Ker...
WCE
2007
14 years 11 months ago
Avoiding Hazards for Speed-Independent Logic Design
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
Igor Lemberski