Sciweavers

287 search results - page 37 / 58
» Reversible logic circuit synthesis
Sort
View
ENTCS
2007
130views more  ENTCS 2007»
14 years 10 months ago
Specify, Compile, Run: Hardware from PSL
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
Roderick Bloem, Stefan Galler, Barbara Jobstmann, ...
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
15 years 6 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
DATE
2000
IEEE
82views Hardware» more  DATE 2000»
15 years 2 months ago
Constructive Library-Aware Synthesis Using Symmetries
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...
Victor N. Kravets, Karem A. Sakallah
DAC
2006
ACM
15 years 11 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
VLSID
1997
IEEE
112views VLSI» more  VLSID 1997»
15 years 2 months ago
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...
James Jacob, P. Srinivas Sivakumar, Vishwani D. Ag...