287 search results - page 39 / 58 » Reversible logic circuit synthesis |
ICCAD
1997
IEEE
15 years 2 months ago
1997
IEEE
In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
ISQED
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. ...
113
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EH
2000
IEEE
15 years 2 months ago
2000
IEEE
Evolvable Hardware (EHW) refers to HW design and selfreconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing ...
102
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CSREAESA
2003
14 years 11 months ago
2003
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...