287 search results - page 48 / 58 » Reversible logic circuit synthesis |
ASYNC
2000
IEEE
15 years 2 months ago
2000
IEEE
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
AHS
2007
IEEE
15 years 4 months ago
2007
IEEE
System-on-Chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid syst...
ISSS
1998
IEEE
15 years 2 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...