Sciweavers

287 search results - page 51 / 58
» Reversible logic circuit synthesis
Sort
View
ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
14 years 1 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
DAC
2000
ACM
15 years 11 months ago
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima...
FPGA
2007
ACM
106views FPGA» more  FPGA 2007»
15 years 4 months ago
A synthesizable datapath-oriented embedded FPGA fabric
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai ...
ICCAD
2007
IEEE
102views Hardware» more  ICCAD 2007»
15 years 6 months ago
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important r...
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang H...
DAC
2001
ACM
15 years 11 months ago
Circuit-based Boolean Reasoning
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi