287 search results - page 53 / 58 » Reversible logic circuit synthesis |
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FPGA
2006
ACM
15 years 1 months ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DAC
2008
ACM
15 years 11 months ago
2008
ACM
Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written...
KCAP
2003
ACM
15 years 3 months ago
2003
ACM
While existing learning techniques can be viewed as inducing programs from examples, most research has focused on rather narrow classes of programs, e.g., decision trees or logic ...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...