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» Reversible logic for supercomputing
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ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 7 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 1 months ago
Debugging of Toffoli networks
—Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible lo...
Robert Wille, Daniel Große, Stefan Frehse, G...
IUI
2012
ACM
12 years 1 months ago
Automatic reverse engineering of interactive dynamic web applications to support adaptation across platforms
The effort and time required to develop user interface models has been one of the main limitations to the adoption of model-based approaches, which enable intelligent processing o...
Federico Bellucci, Giuseppe Ghiani, Fabio Patern&o...
IAJIT
2010
150views more  IAJIT 2010»
13 years 4 months ago
Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology
: In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable a...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
SC
2005
ACM
13 years 11 months ago
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
As device scales shrink, higher transistor counts are available while soft-errors, even in logic, become a major concern. A new class of architectures, such as Merrimac and the IB...
Mattan Erez, Nuwan Jayasena, Timothy J. Knight, Wi...