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DATE
2006
IEEE
124views Hardware» more  DATE 2006»
15 years 9 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
CP
2003
Springer
15 years 8 months ago
Solving Max-SAT as Weighted CSP
For the last ten years, a significant amount of work in the constraint community has been devoted to the improvement of complete methods for solving soft constraints networks. We ...
Simon de Givry, Javier Larrosa, Pedro Meseguer, Th...
SEW
2003
IEEE
15 years 8 months ago
Instrumentation of Intermediate Code for Runtime Verification
Runtime monitoring is aimed at ensuring correct runtime behavior with respect to specified constraints. It provides assurance that properties are maintained during a given program...
Ann Q. Gates, Oscar Mondragon, Mary Payne, Steve R...
FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
16 years 4 hour ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
15 years 8 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber