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MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
15 years 4 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
SIGMETRICS
1998
ACM
114views Hardware» more  SIGMETRICS 1998»
15 years 4 months ago
Generating Representative Web Workloads for Network and Server Performance Evaluation
One role for workload generation is as a means for understanding how servers and networks respond to variation in load. This enables management and capacity planning based on curr...
Paul Barford, Mark Crovella
LCTRTS
1998
Springer
15 years 4 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
POS
1998
Springer
15 years 4 months ago
Optimizing the Read and Write Barriers for Orthogonal Persistence
Persistent programming languages manage volatile memory as a cache for stable storage, imposing a read barrier on operations that access the cache, and a write barrier on updates ...
Antony L. Hosking, Nathaniel Nystrom, Quintin I. C...
ICMCS
1997
IEEE
142views Multimedia» more  ICMCS 1997»
15 years 4 months ago
A Rate Allocation Policy with MCR/PCR Support and Distributed ABR Implementation Using Explicit Rate Feedback
An important concept in the available bit rate (ABR) service model as defined by the ATM Forum is the minimum cell rate (MCR) guarantee as well as the peak cell rate (PCR) constra...
Yiwei Thomas Hou, Henry H.-Y. Tzeng, Shivendra S. ...