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ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
16 years 9 days ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
MOMPES
2008
IEEE
16 years 9 days ago
Architectural Concurrency Equivalence with Chaotic Models
During its lifetime, embedded systems go through multiple changes to their runtime architecture. That is, threads, processes, and processor are added or removed to/from the softwa...
Dionisio de Niz
RTAS
2008
IEEE
16 years 8 days ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
RTAS
2008
IEEE
16 years 8 days ago
A Modular Worst-case Execution Time Analysis Tool for Java Processors
Recent technologies such as the Real-Time Specification for Java promise to bring Java’s advantages to real-time systems. While these technologies have made Java more predictab...
Trevor Harmon, Martin Schoeberl, Raimund Kirner, R...
GLOBECOM
2007
IEEE
16 years 7 days ago
An Analytical Model for a Book-Ahead Bandwidth Scheduler
— Optical networks with book-ahead bandwidth schedulers are being deployed to meet the high-speed and predictable-service networking requirements of applications in the scienti...
Xiangfei Zhu, Mark E. McGinley, Tao Li, Malathi Ve...