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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 11 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
CODES
2008
IEEE
15 years 7 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...
CN
2002
77views more  CN 2002»
15 years 5 months ago
Architecture of a Web server accelerator
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
Junehwa Song, Arun Iyengar, Eric Levy-Abegnoli, Da...
MOBICOM
2009
ACM
16 years 12 days ago
A quorum-based framework for establishing control channels in dynamic spectrum access networks
Establishing a control channel for medium access control is a challenging problem in multi-channel and dynamic spectrum access (DSA) networks. In the design of multi-channel MAC p...
Kaigui Bian, Jung Min Park, Ruiliang Chen
GECCO
2008
Springer
138views Optimization» more  GECCO 2008»
15 years 7 months ago
Modular neuroevolution for multilegged locomotion
Legged robots are useful in tasks such as search and rescue because they can effectively navigate on rugged terrain. However, it is difficult to design controllers for them that ...
Vinod K. Valsalam, Risto Miikkulainen