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» Robust system level design with analog platforms
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ISLPED
2009
ACM
110views Hardware» more  ISLPED 2009»
15 years 4 months ago
End-to-end validation of architectural power models
While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper, we examine the accurac...
Madhu Saravana Sibi Govindan, Stephen W. Keckler, ...
IJVR
2007
124views more  IJVR 2007»
14 years 9 months ago
The Effect of Gaps Between Displays on Spatial Perception and Cognition Tasks in Virtual Environments
—We propose the concept of Gap Between Displays (GBD) as a component of immersion in virtual environment systems. We hypothesized that GBD may reduce users’ task performance in...
Yi Wang, Kunmi Otitoju, Tong Liu, Sijung Kim, Doug...
DAC
2001
ACM
15 years 11 months ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...
IUI
2006
ACM
15 years 3 months ago
Splitting rules for graceful degradation of user interfaces
This paper addresses the problem of the graceful degradation of user interfaces where an initial interface is transferred to a smaller platform. It presents a technique for pagina...
Murielle Florins, Francisco Montero Simarro, Jean ...
DATE
2004
IEEE
97views Hardware» more  DATE 2004»
15 years 1 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu