Sciweavers

14 search results - page 2 / 3
» Robust testability of primitive faults using test points
Sort
View
78
Voted
VTS
2007
IEEE
143views Hardware» more  VTS 2007»
15 years 3 months ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang
ISSTA
2004
ACM
15 years 2 months ago
Testing of java web services for robustness
This paper presents a new compile-time analysis that enables a testing methodology for white-box coverage testing of error recovery code (i.e., exception handlers) in Java web ser...
Chen Fu, Barbara G. Ryder, Ana Milanova, David Won...
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
15 years 1 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
80
Voted
SP
2007
IEEE
15 years 3 months ago
Using Rescue Points to Navigate Software Recovery
We present a new technique that enables software recovery in legacy applications by retrofitting exception-handling capabilities, error virtualization using rescue points. We int...
Stelios Sidiroglou, Oren Laadan, Angelos D. Keromy...
DAC
1995
ACM
15 years 1 months ago
The Validity of Retiming Sequential Circuits
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Ro...