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74
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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
CASES
2008
ACM
14 years 11 months ago
VESPA: portable, scalable, and flexible FPGA-based vector processors
While soft processors are increasingly common in FPGAbased embedded systems, it remains a challenge to scale their performance. We propose extending soft processor instruction set...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
COLING
2008
14 years 11 months ago
The Effect of Syntactic Representation on Semantic Role Labeling
Almost all automatic semantic role labeling (SRL) systems rely on a preliminary parsing step that derives a syntactic structure from the sentence being analyzed. This makes the ch...
Richard Johansson, Pierre Nugues
MEDIAFORENSICS
2010
14 years 11 months ago
Improving re-sampling detection by adding noise
Current image re-sampling detectors can reliably detect re-sampling in JPEG images only up to a Quality Factor (QF) of 95 or higher. At lower QFs, periodic JPEG blocking artifacts...
Lakshmanan Nataraj, Anindya Sarkar, B. S. Manjunat...
93
Voted
NIPS
2008
14 years 11 months ago
Partially Observed Maximum Entropy Discrimination Markov Networks
Learning graphical models with hidden variables can offer semantic insights to complex data and lead to salient structured predictors without relying on expensive, sometime unatta...
Jun Zhu, Eric P. Xing, Bo Zhang