768 search results - page 86 / 154 » Robustness of Sequential Circuits |
106
Voted
AHS
2006
IEEE
15 years 6 months ago
2006
IEEE
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
112
Voted
ICCAD
2009
IEEE
14 years 10 months ago
2009
IEEE
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
131
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CHES
2011
Springer
14 years 15 days ago
2011
Springer
Abstract. The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Meta...
109
click to vote
SAC
2006
ACM
15 years 6 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
96
Voted
ASPDAC
2008
ACM
15 years 2 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...