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» Route Packets, Not Wires: On-Chip Interconnection Networks
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111
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ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
15 years 8 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
83
Voted
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
15 years 5 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
ESTIMEDIA
2006
Springer
15 years 3 months ago
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
92
Voted
TC
2008
14 years 11 months ago
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an im...
Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Ken...
TC
2010
14 years 10 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum