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» Route Packets, Not Wires: On-Chip Interconnection Networks
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FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
15 years 3 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
ICCAD
2006
IEEE
122views Hardware» more  ICCAD 2006»
15 years 6 months ago
Network coding for routability improvement in VLSI
With the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links....
Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulat...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
15 years 4 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
15 years 4 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
IPPS
1996
IEEE
15 years 1 months ago
Adaptive Source Routing in Multistage Interconnection Networks
We describe the adaptive source routing (ASR) method which is a first attempt to combine adaptive routing and source routing methods. In ASR, the adaptivity of each packet is dete...
Yucel Aydogan, Craig B. Stunkel, Cevdet Aykanat, B...