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» Router designs for elastic buffer on-chip networks
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CAL
2008
13 years 4 months ago
Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. Howev...
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, ...
TRIDENTCOM
2006
IEEE
14 years 7 days ago
Emulation versus simulation: A case study of TCP-targeted denial of service attacks
—In this paper, we investigate the applicability of simulation and emulation for denial of service (DoS) attack experimentation. As a case study, we consider low-rate TCP-targete...
Roman Chertov, Sonia Fahmy, Ness B. Shroff
ISPASS
2009
IEEE
14 years 1 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
LCN
2005
IEEE
13 years 11 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
PE
2008
Springer
173views Optimization» more  PE 2008»
13 years 6 months ago
Improving fairness in a WRED-based DiffServ network: A fluid-flow approach
The DiffServ architecture has been proposed as a scalable approach for upgrading the Internet, adding service differentiation functionalities. However, several aspects of this arc...
Mario Barbera, Alfio Lombardo, Giovanni Schembra, ...