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» Routing Lookups in Hardware at Memory Access Speeds
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TON
2010
138views more  TON 2010»
14 years 6 months ago
SUSE: superior storage-efficiency for routing tables through prefix transformation and aggregation
Abstract--A novel storage design for IP routing table construction is introduced on the basis of a single set-associative hash table to support fast longest prefix matching (LPM). ...
Fong Pong, Nian-Feng Tzeng
JSW
2007
126views more  JSW 2007»
14 years 11 months ago
Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware
— The paper addresses software and firmware implementation of multiple-output Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means ...
Vaclav Dvorak
55
Voted
ISMVL
1996
IEEE
76views Hardware» more  ISMVL 1996»
15 years 3 months ago
A Multiple-Valued Ferroelectric Content-Addressable Memory
A novel architecturefor a Multiple-Valued Ferroelectric Content-Addressable Memory (FCAM) is proposed. An FCAM employs ferroelectric capacitors as storage elements to provide a no...
Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu
81
Voted
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
14 years 9 months ago
Energy and performance driven circuit design for emerging phase-change memory
Abstract--Phase-Change Random Access Memory (PRAM) has become one of the most promising emerging memory technologies, due to its attractive features such as high density, fast acce...
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 4 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu