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» Routing Lookups in Hardware at Memory Access Speeds
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EUROPAR
1995
Springer
15 years 3 months ago
Bounds on Memory Bandwidth in Streamed Computations
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...
Sally A. McKee, William A. Wulf, Trevor C. Landon
WMPI
2004
ACM
15 years 5 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
92
Voted
ISCAS
2005
IEEE
156views Hardware» more  ISCAS 2005»
15 years 5 months ago
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due...
Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubm...
VTS
2007
IEEE
103views Hardware» more  VTS 2007»
15 years 6 months ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
IPPS
2000
IEEE
15 years 4 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda