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» Routing Lookups in Hardware at Memory Access Speeds
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ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
15 years 6 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi
86
Voted
CCS
2009
ACM
15 years 6 months ago
Secure in-VM monitoring using hardware virtualization
Kernel-level attacks or rootkits can compromise the security of an operating system by executing with the privilege of the kernel. Current approaches use virtualization to gain hi...
Monirul I. Sharif, Wenke Lee, Weidong Cui, Andrea ...
LCTRTS
2007
Springer
15 years 5 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
126
Voted
BMCBI
2008
214views more  BMCBI 2008»
14 years 12 months ago
Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
Yoginder S. Dandass, Shane C. Burgess, Mark Lawren...
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
15 years 4 months ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...