149 search results - page 19 / 30 » Routing Lookups in Hardware at Memory Access Speeds |
ASPLOS
1998
ACM
15 years 4 months ago
1998
ACM
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
103
Voted
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
99
Voted
DSD
2010
IEEE
14 years 12 months ago
2010
IEEE
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
CCGRID
2010
IEEE
14 years 10 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
WMPI
2004
ACM
15 years 5 months ago
2004
ACM
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. ...