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» Routing Lookups in Hardware at Memory Access Speeds
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FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
15 years 3 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
14 years 9 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
MICRO
2009
IEEE
159views Hardware» more  MICRO 2009»
15 years 6 months ago
Adaptive line placement with the set balancing cache
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 6 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ARCS
2004
Springer
15 years 3 months ago
STAFF: State Transition Applied Fast Flash Translation Layer
Abstract. Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption....
Tae-Sun Chung, Stein Park, Myung-Jin Jung, Bumsoo ...