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» Routing Lookups in Hardware at Memory Access Speeds
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MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
15 years 6 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
VLSI
2007
Springer
15 years 5 months ago
A low-power deblocking filter architecture for H.264 advanced video coding
Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking ...
Jaemoon Kim, Sangkwon Na, Chong-Min Kyung
ISLPED
2003
ACM
88views Hardware» more  ISLPED 2003»
15 years 5 months ago
Reducing data cache energy consumption via cached load/store queue
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
DEBU
2010
128views more  DEBU 2010»
14 years 9 months ago
Designing Database Operators for Flash-enabled Memory Hierarchies
Flash memory affects not only storage options but also query processing. In this paper, we analyze the use of flash memory for database query processing, including algorithms that...
Goetz Graefe, Stavros Harizopoulos, Harumi A. Kuno...
EH
1999
IEEE
161views Hardware» more  EH 1999»
15 years 4 months ago
Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
John F. McDonald, Bryan S. Goda