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» Routing Lookups in Hardware at Memory Access Speeds
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TVLSI
2008
139views more  TVLSI 2008»
14 years 11 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
GLOBECOM
2010
IEEE
14 years 9 months ago
Skip Finite Automaton: A Content Scanning Engine to Secure Enterprise Networks
Abstract--Today's file sharing networks are creating potential security problems to enterprise networks, i.e., the leakage of confidential documents. In order to prevent such ...
Junchen Jiang, Yi Tang, Bin Liu, Yang Xu, Xiaofei ...
JPDC
2006
111views more  JPDC 2006»
14 years 11 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
15 years 6 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
SC
1995
ACM
15 years 3 months ago
Index Array Flattening Through Program Transformation
This paper presents techniques for compiling loops with complex, indirect array accesses into loops whose array references have at most one level of indirection. The transformatio...
Raja Das, Paul Havlak, Joel H. Saltz, Ken Kennedy