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» Routing Lookups in Hardware at Memory Access Speeds
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DATE
2007
IEEE
160views Hardware» more  DATE 2007»
15 years 6 months ago
FPGA-based networking systems for high data-rate and reliable in-vehicle communications
The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automot...
Sergio Saponara, Esa Petri, Marco Tonarelli, Iacop...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 4 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
15 years 6 months ago
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederi...
ICPP
2003
IEEE
15 years 5 months ago
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...
Xiaotong Zhuang, Hsien-Hsin S. Lee
PLDI
1999
ACM
15 years 4 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus