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ISVLSI
2003
IEEE
97views VLSI» more  ISVLSI 2003»
15 years 10 months ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
Andrew B. Kahng, Bao Liu
160
Voted
SASN
2003
ACM
15 years 10 months ago
SECTOR: secure tracking of node encounters in multi-hop wireless networks
In this paper we present SECTOR, a set of mechanisms for the secure verification of the time of encounters between nodes in multi-hop wireless networks. This information can be u...
Srdjan Capkun, Levente Buttyán, Jean-Pierre...
123
Voted
SLIP
2003
ACM
15 years 10 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
139
Voted
IPSN
2003
Springer
15 years 10 months ago
A Collaborative Approach to In-Place Sensor Calibration
Abstract. Numerous factors contribute to errors in sensor measurements. In order to be useful, any sensor device must be calibrated to adjust its accuracy against the expected meas...
Vladimir Bychkovskiy, Seapahn Megerian, Deborah Es...
IPTPS
2003
Springer
15 years 10 months ago
PeerNet: Pushing Peer-to-Peer Down the Stack
- An unwritten principle of the Internet Protocol is that the IP address of a node also serves as its identifier. We observe that many scalability problems result from this princi...
Jakob Eriksson, Michalis Faloutsos, Srikanth V. Kr...